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D a t a S h e e t , Rev. 1.0, Oct. 2004
HYS64T32000HDL-[3.7/5]-A HYS64T64020HDL-[3.7/5]-A HYS64T128021HDL-[3.7/5]-A
200-Pin SO-DIMM DDR2 SDRAM Modules DDR2 SDRAM RoHS Compliant
Memory Products
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The information in this document is subject to change without notice. Edition 2004-10 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
D a t a S h e e t , Rev. 1.0, Oct. 2004
HYS64T32000HDL-[3.7/5]-A HYS64T64020HDL-[3.7/5]-A HYS64T128021HDL-[3.7/5]-A
200-Pin SO-DIMM DDR2 SDRAM Modules DDR2 SDRAM SO-DIMM SDRAM RoHS Compliant
Memory Products
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thinking.
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Revision History: Previous Revision: Page All 20, 21 Rev. 1.0 Rev. 0.87 2004-10 2003-06
Subjects (major changes since last revision) Layout and paragraph-order update
IDD currents updated and final
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
Template: mp_a4_v2.3_2004-01-14.fm
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
Table of Contents 1 1.1 1.2 2 2.1 3 3.1 3.2 4 4.1 5 6 7 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 22 On Die Termination (ODT) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
IDD Specifications and Conditions
IDD Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Product Type Nomenclature (DDR2 DRAMs and DIMMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Data Sheet
5
Rev. 1.0, 2004-10 09122003-FTXN-KM26
200-Pin SO-DIMM DDR2 SDRAM Modules DDR2 SDRAM
HYS64T32000HDL-[3.7/5]-A HYS64T64020HDL-[3.7/5]-A HYS64T128021HDL-[3.7/5]-A
1
Overview
This chapter gives an overview of the 1.8 V Unbuffered 200-Pin SO-DIMM DDR2 SDRAM Modules product family and describes its main characteristics.
1.1
*
Features
* * * * * * * * Programmable CAS Latencies (3, 4 and 5), Burst Length (8 & 4) and Burst Type Auto Refresh (CBR) and Self Refresh All inputs and outputs SSTL_18 compatible Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT) Serial Presence Detect with E2PROM SO-DIMM Dimensions (nominal): 30 mm high, 67.6 mm wide Based on JEDEC standard reference layouts Raw Card "A", "C" and "D" RoHS Compliant Products1)
* * *
200-Pin PC2-4200 and PC2-3200 DDR2 SDRAM memory modules for use as main memory when installed in systems such as mobile personal computers. 32M x 64, 64M x 64 and 128M x 64 module organization, and 32M x 16, 64M x 8 chip organization JEDEC standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V ( 0.1 V) power supply Built with 512 Mb DDR2 SDRAMs in P-TFBGA-84, P-TFBGA-60 chipsize packages Performance -3.7
Table 1
Product Type Speed Code Speed Grade max. Clock Frequency @CL5 @CL4 @CL3 min. RAS-CAS-Delay min. Row Precharge Time min. Row Active Time min. Row Cycle Time
-5 PC2-3200 3-3-3 200 200 200 15 15 40 55
Units -- MHz MHz MHz ns ns ns ns
PC2-4200 4-4-4
fCK5 fCK4 fCK3 tRCD tRP tRAS tRC
266 266 200 15 15 45 60
1)RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Data Sheet
6
Rev. 1.0, 2004-10 09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
Overview
1.2
Description
The memory array is designed with 512Mb DoubleData-Rate-Two (DDR2) Synchronous DRAMs. Decoupling capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.
The INFINEON HYS64T[32/64/128]0xxHDL-[3.7/5]-A module family are Small Outline DIMM modules "SODIMMs" with 30,0 mm height based on DDR2 technology. DIMMs are available as non-ECC modules in 32M x 64 (256MB), 64M x 64 (512MB), 128M x 64 (1GB) organisation and density, intended for mounting into 200 pin connector sockets.
Table 2
Ordering Informationfor RoHS Compliant Products Compliance Code2) Description SDRAM Technology 512 Mbit (x16) 512 Mbit (x16 512 Mbit (x8) 512 Mbit (x16) 512 Mbit (x16 512 Mbit (x8)
Product Type1) PC2-3200 HYS64T32000HDL-5-A HYS64T64020HDL-5-A HYS64T128021HDL-5-A PC2-4200 HYS64T32000HDL-3.7-A HYS64T64020HDL-3.7-A
256MB 1Rx16 PC2-3200S-333-11-C0 512MB 2Rx16 PC2-3200S-333-11-A0 1GB 2Rx8 PC2-3200S-333-11-D0 256MB 1Rx16 PC2-4200S-444-11-C0 512MB 2Rx16 PC2-4200S-444-11-A0
1 rank, Non-ECC 2 ranks, Non-ECC 2 ranks, Non-ECC 1 rank, Non-ECC 2 ranks, Non-ECC 2 ranks, Non-ECC
HYS64T128021HDL-3.7-A 1GB 2Rx8 PC2-4200S-444-11-F0
1) All part numbers end with a place code, designating the silicon die revision. Example: HYS64T32000HDL-5-A, indicating Rev. "A" dies are used for DDR2 SDRAM components. For all INFINEON DDR2 module and component nomenclature see Chapter 7 of this data sheet. 2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2-4200S-444-11- C1", where 4200S means SO-DIMM modules with 4.26 GB/sec Module Bandwidth and "444-11" means Column Address Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.1 and produced on the Raw Card "C".
Table 3 DIMM Density
Address Format Module Organization Memory Ranks 1 2 2 ECC/ Non-ECC Non-ECC Non-ECC Non-ECC # of SDRAMs 4 8 16 # of row/bank/columns bits Raw Card 13/2/10 14/2/10 14/2/10 C A F
256 MByte 32M x64 512 MByte 64M x64 1 GByte Table 4 128M x64
Components on Modules1) DRAM Components2) HYB18T512160AF HYB18T512160AF HYB18T512800AF DRAM Density 512 Mbit 512 Mbit 512 Mbit DRAM Organisation 32M x16 32M x16 64Mb x8
Product Type2) HYS64T32000HDL HYS64T64020HDL HYS64T128021HDL
2) Green Product
1) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Data Sheet
7
Rev. 1.0, 2004-10 09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
Pin Configuration
2
Pin Configuration
The pin configuration of the Small Outline DDR2 SDRAM DIMM is listed by function in Table 5 (200 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin numbering is depicted in Figure 1 Table 5 Pin# Clock Signals 30 164 32 166 CK0 CK1 CK0 CK1 I I I I SSTL SSTL SSTL SSTL Clock Signals 2:0, Complement Clock Signals 2:0 Note: The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and the falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. Clock Enable Rank 1:0 Note: Activates the DDR2 SDRAM CK signal when HIGH and deactivates the CK signal when LOW. By deactivating the clocks, CKE LOW initiates the Power Down Mode or the Self Refresh Mode. Note: 2 Ranks module NC Control Signals 110 115 S0 S1 I I SSTL SSTL Chip Select Rank 1:0 Note: Enables the associated DDR2 SDRAM command decoder when LOW and disables the command decoder when HIGH. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1. Ranks are also called "Physical banks". Note: 2 Ranks module NC 108 RAS NC I -- SSTL Note: 1-rank module Row Address Strobe Note: When sampled at the cross point of the rising edge of CK,and falling edge of CK, RAS, CAS and WE define the operation to be executed by the SDRAM. 113 109 Address Signals 107 106 BA0 BA1 I I SSTL SSTL Bank Address Bus 2:0 Note: Selects which DDR2 SDRAM internal bank of four or eight is activated. CAS WE I I SSTL SSTL Column Address Strobe Write Enable NC -- Note: 1-rank module Pin Configuration of SO-DIMM Name Pin Type Buffer Type Function
79 80
CKE0 CKE1
I I
SSTL SSTL
Data Sheet
8
Rev. 1.0, 2004-10 09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
Pin Configuration Table 5 Pin# 85 Pin Configuration of SO-DIMM (cont'd) Name BA2 NC 102 101 100 99 98 97 94 92 93 91 105 90 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 Pin Type I I I I I I I I I I I I I I I Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Function Bank Address Bus 2 Note: greater than 512Mb DDR2 SDRAMS Note: less than 1Gb DDR2 SDRAMS Address Bus 12:0 Note: During a Bank Activate command cycle, defines the row address when sampled at the crosspoint of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is HIGH, autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is LOW, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is HIGH, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is LOW, then BA0-BAn are used to define which bank to precharge. Address Signal 12 Note: Module based on 256 Mbit or larger dies 116 A13 NC Data Signals 5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Bus 63:0 Note: Data Input/Output pins I NC SSTL -- Address Signal 13 Note: 1 Gbit based module Note: Module based on 512 Mbit or smaller dies
89
A12
I
SSTL
Data Sheet
9
Rev. 1.0, 2004-10 09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
Pin Configuration Table 5 Pin# 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 Data Sheet Pin Configuration of SO-DIMM (cont'd) Name DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL 10 Rev. 1.0, 2004-10 09122003-FTXN-KM26 Function Data Bus 63:0
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
Pin Configuration Table 5 Pin# 176 179 181 189 191 180 182 192 194 Data Strobe Signals 13 11 31 29 51 49 70 68 131 129 148 146 169 167 188 186 Data Mask Signals 10 26 52 67 130 147 170 185 EEPROM 197 SCL I CMOS Serial Bus Clock Note: This signal is used to clock data into and out of the SPD EEPROM. DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 I I I I I I I I SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Mask Bus 7:0 Note: The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is LOW but blocks the write operation if it is HIGH. In Read mode, DM lines have no effect. DQS0 DQS0 DQS1 DQS1 DQS2 DQS2 DQS3 DQS3 DQS4 DQS4 DQS5 DQS5 DQS6 DQS6 DQS7 DQS7 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Strobe Bus 7:0 Note: The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode the data strobe is sourced by the DDR2 SDRAM and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS. If the module is to be operated in single ended strobe mode, all DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers programmed appropriately. Pin Configuration of SO-DIMM (cont'd) Name DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Function Data Bus 63:0
Data Sheet
11
Rev. 1.0, 2004-10 09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
Pin Configuration Table 5 Pin# 195 Pin Configuration of SO-DIMM (cont'd) Name SDA Pin Type I/O Buffer Type OD Function Serial Bus Data Note: This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be connected from SDA to to VDDSPD on the motherboard to act as a pull-up. 198 200 Power Supplies 1 199 SA0 SA1 I I CMOS CMOS Serial Address Select Bus 1:0 Note: Address pins used to select the Serial Presence Detect base address. I/O Reference Voltage Note: Reference voltage for the SSTL-18 inputs. EEPROM Power Supply Note: Power supplies for core, I/O, Serial Presence Detect, and ground for the module. 81,82,87,88,95,96,103,104, 111,112,117,118
VREF
AI
--
VDDSPD PWR --
VDD
PWR
--
Power Supply Note: Power supplies for core, I/O, Serial Presence Detect, and ground for the module.
2,3,8,9,12,15,18,21,24,27,28, VSS 33,34,39,40,41,42,47,48,53, 54,59,60,65,66,71,72,77,78, 121,122,127,128,132,133,138, 139,144,145,149,150,155,156, 161,162,165,171,172,177, 178,183,184,187,190,193,196 Other Pins 114 119 ODT0 ODT1
GND
--
Ground Plane Note: Power supplies for core, I/O, Serial Presence Detect, and ground for the module.
I I
SSTL SSTL
On-Die Termination Control 1:0 On-Die Termination Control 1 Note: Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR2 SDRAM mode register. Note: 2 Rank modules
NC 50,69,83,84,120,163,168 NC
NC NC
-- --
Note: 1 Rank modules Not connected Note: Pins not connected on Infineon SO-DIMMs
Data Sheet
12
Rev. 1.0, 2004-10 09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
Pin Configuration
Table 6
Abbreviation I O I/O AI PWR GND NC
Abbreviations for Pin Type
Description Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Connected
Table 7 Abbreviation SSTL LV-CMOS
Abbreviations for Buffer Type Description Serial Stub Terminated Logic (SSTL_18) Low Voltage CMOS
CMOS
OD
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
Data Sheet
13
Rev. 1.0, 2004-10 09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
Pin Configuration
V REF DQ0 V SS DQS0 DQ2 V SS DQ9 DQS1 V SS DQ11 -
Pin 001 Pin 005 Pin 009 Pin 013 Pin 017 Pin 021 Pin 025 Pin 029 Pin 033 Pin 037
V SS DQ1 DQS0 V SS DQ3 DQ8 V SS DQS1 DQ10 V SS -
Pin 003 Pin 007 Pin 011 Pin 015 Pin 019 Pin 023 Pin 027 Pin 031 Pin 035 Pin 039
Pin 004 Pin 008 Pin 012 Pin 016 Pin 020 Pin 024 Pin 028 Pin 032 Pin 036 Pin 040
- DQ4 - VSS - VSS - DQ7 - DQ12 - VSS - VSS - CK0 - DQ14 - VSS
Pin 002 Pin 006 Pin 010 Pin 014 Pin 018 Pin 022 Pin 026 Pin 030 Pin 034 Pin 038
-
VSS DQ5 DM0 DQ6 VSS DQ13 DM1 CK0 VSS DQ15
V SS DQ17 DQS2 V SS DQ19 DQ24 V SS NC DQ26 V SS VDD NC/BA2 A12 A8 A5 A1 A10/AP WE CAS VDD V SS DQ33 DQS4 V SS DQ35 DQ40 V SS V SS DQ43 DQ48 V SS V SS DQS6 DQ50 V SS DQ57 DM7 DQ58 V SS SCL -
Pin 041 Pin 045 Pin 049 Pin 053 Pin 057 Pin 061 Pin 065 Pin 069 Pin 073 Pin 077 Pin 081 Pin 085 Pin 089 Pin 093 Pin 097 Pin 101 Pin 105 Pin 109 Pin 113 Pin 117 Pin 121 Pin 125 Pin 129 Pin 133 Pin 137 Pin 141 Pin 145 Pin 149 Pin 153 Pin 157 Pin 161 Pin 165 Pin 169 Pin 173 Pin 177 Pin 181 Pin 185 Pin 189 Pin 193 Pin 197
DQ16 V SS DQS2 DQ18 V SS DQ25 DM3 V SS DQ27 CKE0 NC VDD A9 VDD A3 VDD BA0 VDD NC/S1 NC/ODT1 DQ32 V SS DQS4 DQ34 V SS DQ41 DM5 DQ42 V SS DQ49 NC DQS6 V SS DQ51 DQ56 V SS V SS DQ59 SDA V DDSPD -
Pin 043 Pin 047 Pin 051 Pin 055 Pin 059 Pin 063 Pin 067 Pin 071 Pin 075 Pin 079 Pin 083 Pin 087 Pin 091 Pin 095 Pin 099 Pin 103 Pin 107 Pin 111 Pin 115 Pin 119 Pin 123 Pin 127 Pin 131 Pin 135 Pin 139 Pin 143 Pin 147 Pin 151 Pin 155 Pin 159 Pin 163 Pin 167 Pin 171 Pin 175 Pin 179 Pin 183 Pin 187 Pin 191 Pin 195 Pin 199
Pin 044 Pin 048 Pin 052 Pin 056 Pin 060 Pin 064 Pin 068 Pin 072 Pin 076 Pin 080 Pin 084 Pin 088 Pin 092 Pin 096 Pin 100 Pin 104 Pin 108 Pin 112 Pin 116 Pin 120 Pin 124 Pin 128 Pin 132 Pin 136 Pin 140 Pin 144 Pin 148 Pin 152 Pin 156 Pin 160 Pin 164 Pin 168 Pin 172 Pin 176 Pin 180 Pin 184 Pin 188 Pin 192 Pin 196 Pin 200
-
DQ20 VSS DM2 DQ22 VSS DQ29 DQS3 VSS DQ31 NC/CKE1 NC VDD A7 VDD A2 VDD RAS VDD NC/A13 NC DQ36 VSS VSS DQ39 DQ44 VSS DQS5 DQ46 VSS DQ53 CK1 VSS VSS DQ55 DQ60 VSS DQS7 DQ62 VSS SA1
Pin 042 Pin 046 Pin 050 Pin 054 Pin 058 Pin 062 Pin 066 Pin 070 Pin 074 Pin 078 Pin 082 Pin 086 Pin 090 Pin 094 Pin 098 Pin 102 Pin 106 Pin 110 Pin 114 Pin 118 Pin 122 Pin 126 Pin 130 Pin 134 Pin 138 Pin 142 Pin 146 Pin 150 Pin 154 Pin 158 Pin 162 Pin 166 Pin 170 Pin 174 Pin 178 Pin 182 Pin 186 Pin 190 Pin 194 Pin 198
-
VSSDDD DQ21 NC VSS DQ23 DQ28 VSS DQS3 DQ30 VSS VDD NC/A14 A11 A6 A4 A0 BA1 S0 ODT0 VDD VSS DQ37 DM4 DQ38 VSS DQ45 DQS5 VSS DQ47 DQ52 VSS CK1 DM6 DQ54 VSS DQ61 DQS7 VSS DQ63 SA0 MPPT0140
FRONTSIDE
Figure 1
Pin Configuration SO-DIMM (200 Pin)
Data Sheet
14
BACKSIDE
Rev. 1.0, 2004-10 09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
Pin Configuration
2.1
%$ %$ $ $Q 5$6 &$6 :( &.( &.( 2'7 2'7 &. &. &. &. 6 6 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4
Block Diagrams
%$ %$ 6'5$0V ' ' $ $Q 6'5$0V ' ' 5$6 6'5$0V ' ' &$6 6'5$0V ' ' :( 6'5$0V ' ' &.( 6'5$0V ' ' &.( 6'5$0V ' ' 2'7 6'5$0V ' ' 2'7 6'5$0V ' ' ORDGV ORDGV 9''63' 9''9''4 95() 966 9'' 63' ((3520 ( 9''9''4 6'5$0V ' ' 95() 6'5$0V ' ' 966 6'5$0V ' ' 6&/ 6'$ 6$ 6$ 6&/ 6'$ $ $ $ :3 9VV /'0 &6 /'46 /'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 8'0 8'46 8'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 /'0 &6 /'46 /'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 8'0 8'46 8'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ' /'0 &6 /'46 /'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 8'0 8'46 8'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 /'0 &6 /'46 /'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 8'0 8'46 8'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ' '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 /'0 &6 /'46 /'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 8'0 8'46 8'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 /'0 &6 /'46 /'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 8'0 8'46 8'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ' /'0 &6 /'46 /'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 8'0 8'46 8'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 /'0 &6 /'46 /'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 8'0 8'46 8'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ' (
'
'
'
'
Figure 2 Notes
Block Diagram Raw Card A SO-DIMM (x64, 2 Ranks, x16)
03%7
1. DQ, DQS, DM resistors are 22 5 %
2. S0, S1, BAn, An, RAS, CAS, WE, ODTO, ODT1, CKEO, CKE1 resistors are 3 5 %
Data Sheet
15
Rev. 1.0, 2004-10 09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
Pin Configuration
%$ %$ $ $Q 5$6 &$6 :( &.( 2'7 6 &. &. &. &. 6&/ 6'$ 6$ 6$
%$ %$ 6'5$0V ' ' $ $Q 6'5$0V ' ' 5$6 6'5$0V ' ' &$6 6'5$0V ' ' :( 6'5$0V ' ' &.( 6'5$0V ' ' 2'7 6'5$0V ' ' '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4
9''63' 9''9''4 95() 966
9'' 63' ((3520 ( 9''9''4 6'5$0V ' ' 95() 6'5$0V ' ' 966 6'5$0V ' '
ORDGV ORDGV 6&/ 6'$ $ $ $ :3 (
9VV
/'0 &6 /'46 /'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 8'0 8'46 8'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 /'0 &6 /'46 /'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 8'0 8'46 8'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2
'
'0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4
/'0 &6 /'46 /'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 8'0 8'46 8'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 /'0 &6 /'46 /'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 8'0 8'46 8'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2
'
'
'
03%7
Figure 3 Notes
Block Diagram Raw Card C SO-DIMM (x64, 1Rank, x16) 2. S0, S1, BAn, An, RAS, CAS, WE, ODTO, ODT1, CKEO, CKE1 resistors are 3 5 %
1. DQ, DQS, DM resistors are 22 5 % )
Data Sheet
16
Rev. 1.0, 2004-10 09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
Pin Configuration
BA0 - BA2 A0 - An RAS CAS WE CKE 0 CKE 1 ODT 0 ODT 1 S0 S1 DM0 DQS0 DQS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM1 DQS1 DQS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM2 DQS2 DQS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM3 DQS3 DQS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
BA0 - BA2: SDRAMs D0 - D15 A0 - An: SDRAMs D0 - D15 RAS: SDRAMs D0 - D15 CAS: SDRAMs D0 - D15 WE: SDRAMs D0 - D15 CKE 0: SDRAMs D0 - D1, D4 - D5, D10 - D11, D14 - D15 CKE 1: SDRAMs D2 - D3, D6 - D9, D12 - D13 ODT 0: SDRAMs D0 - D1, D4 - D5, D10 - D11, D14 - D15 ODT 1: SDRAMs D2 - D3, D6 - D9, D12 - D13
VDD,SPD VDD/VDDQ VREF VSS
VDD: SPD EEPROM E0 VDD/VDDQ: SDRAMs D0 - D15 VREF: SDRAMs D0 - D15 VSS: SDRAMs D0 - D15
DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0
DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D8 SCL SDA SA0 SA1 SA2 VSS CK0 CK0 D9 CK1 CK1 SCL SDA A0 A1 A2 WP
E0
5.6 pF 5.6 pF
8 loads
DM4 DQS4 DQS4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM5 DQS5 DQS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM6 DQS6 DQS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM7 DQS7 DQS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D4
DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D12
D1
D5
D13
8 loads
D10
D2
D14
D6
D11
D3
D15
D7
MPBT0370
Figure 4 Notes
Block Diagram Raw Card F SO-DIMM (x64, 2 Ranks, x8) 4. S0, S1, ODTO, ODT1, CKEO, CKE1 resistors are 3 5 % 5. BAn, An, RAS, CAS, WE resistors are 10 5 %
3. DQ, DQS, DM resistors are 22 5 %
Data Sheet
17
Rev. 1.0, 2004-10 09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
IDD Specifications and Conditions
3
Table 8 Parameter
IDD Specifications and Conditions
IDD Measurement Conditions 1)2)3)4)5)6)
Symbol
Operating Current 0 One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
IDD0
Operating Current 1 IDD1 One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, tRCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Precharge Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Precharge Power-Down Current Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2N IDD2P
Precharge Quiet Standby Current IDD2Q All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE, Data bus inputs are FLOATING. Active Standby Current Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA. Active Power-Down Current All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit); Active Power-Down Current All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit); Operating Current Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX., tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
IDD3N
IDD3P(0) IDD3P(1) IDD4R
Operating Current IDD4W Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; Burst Refresh Current IDD5B tCK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Distributed Refresh Current IDD5D tCK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Data Sheet
18
Rev. 1.0, 2004-10 09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
IDD Specifications and Conditions Table 8 Parameter Self-Refresh Current CKE 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 C max.
IDD Measurement Conditions (cont'd)1)2)3)4)5)6)
Symbol
IDD6
All Bank Interleave Read Current IDD7 All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.
1)
VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V 2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled. 3) Definitions for IDD: LOW is defined as VIN VIL(ac).MAX, HIGH is defined as VIN VIH(ac).MIN
STABLE is defined as: inputs are stable at a HIGH or LOW level FLOATING is defined as: inputs are VREF = VDDQ /2 SWITCHING is defined as: inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ signals not including mask or strobes.
4)
IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
5) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P 6) For details and notes see the relevant INFINEON component data sheet
Data Sheet
19
Rev. 1.0, 2004-10 09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
IDD Specifications and Conditions
Table 9
IDD Specification
HYS64T32000HDL-3.7-A HYS64T64020HDL-3.7-A HYS64T128021HD-3.7-A Unit Notes1)
Product Type
Organization
256 MB x64 1 Rank -3.7
512 MB x64 2 Ranks -3.7 Max. 340 380 320 30 240 320 130 40 420 460 540 50 16 900
1 GB x64 2 Ranks -3.7 Max. 550 630 640 60 480 640 260 80 750 790 1070 100 32 1160 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
2) 2) 3) 3) 3) 3) 3) 3) 2) 2) 2) 3) 3) 2)
Symbol
Max. 320 360 160 20 120 160 60 20 400 440 520 20 8 880
IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3N IDD3P(MRS= 0) IDD3P(MRS= 1) IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
1) Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled 2) The other rank is in IDD2P Pre charge Power-Down Standby Current mode 3) Both ranks are in the same IDD current mode
Data Sheet
20
Rev. 1.0, 2004-10 09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
IDD Specifications and Conditions
Table 10
IDD Specification
HYS64T128021HDL-5-A HYS64T32000HDL-5-A HYS64T64020HDL-5-A Unit Notes1)
Product Type
Organization
256 MB x64 1 Rank -5
512 MB x64 2 Ranks -5 Max. 300 320 260 30 200 280 100 40 360 380 500 50 16 860
1 GB x64 2 Ranks -5 Max. 470 510 510 60 400 560 210 80 590 630 990 100 32 1070 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
2) 2) 3) 3) 3) 3) 3) 3) 2) 2) 2) 3) 3) 2)
Symbol
Max. 280 300 130 20 100 140 50 20 340 360 480 20 8 840
IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3N IDD3P(MRS= 0) IDD3P(MRS= 1) IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
1) Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled 2) The other rank is in IDD2P Pre charge Power-Down Standby Current mode 3) Both ranks are in the same IDD current mode
Data Sheet
21
Rev. 1.0, 2004-10 09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
IDD Specifications and Conditions
3.1
IDD Test Conditions
IDD Measurement Test Conditions
Symbol -3.7 4 3.75 15 60 7.5 10 45 70000 15 105 7.8 -5 3 5 15 55 7.5 10 40 70000 15 105 7.8 Unit PC2-4200-4-4-4 PC2-3200-3-3-3
For testing the IDD parameters, the following timing parameters are used: Table 11 Parameter CAS Latency
CL(IDD) Clock Cycle Time tCK(IDD) Active to Read or Write delay tRCD(IDD) Active to Active / Auto-Refresh command period tRC(IDD) 1) Active bank A to Active bank B command delay x8 tRRD(IDD) 2) x16 tRRD(IDD) Active to Precharge Command tRAS.MIN(IDD) tRAS.MAX(IDD) Precharge Command Period tRP(IDD) Auto-Refresh to Active / Auto-Refresh command period tRFC(IDD) Average periodic Refresh interval tREFI
1) For modules based on x8 components 2) For modules based on x16 components
tCK
ns ns ns ns ns ns ns ns ns s
3.2
On Die Termination (ODT) Current
current consumption for any terminated input pin, depends on the input pin is in tristate or driving 0 or 1, as long a ODT is enabled during a given period of time.
The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1). Depending on address bits A[6,2] in the EMRS(1) a "weak" or "strong" termination can be selected. The Table 12 Parameter Enabled ODT current per DQ added IDDQ current for ODT enabled; ODT is HIGH; Data Bus inputs are FLOATING ODT current per terminated pin:
Symbol Min.
Typ. 6 3 12 6
Max. 7.5 3.75 15 7.5
Unit mA/DQ mA/DQ mA/DQ mA/DQ
EMRS(1) State A6 = 0, A2 = 1 A6 = 1, A2 = 0 A6 = 0, A2 = 1 A6 = 1, A2 = 0
IODTO
5 2.5 10 5
IODTT Active ODT current per DQ added IDDQ current for ODT enabled; ODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING.
Note: For power consumption calculations the ODT duty cycle has to be taken into account
Data Sheet
22
Rev. 1.0, 2004-10 09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
Electrical Characteristics
4
4.1
Table 13 Parameter
Electrical Characteristics
Operating Conditions
Absolute Maximum Ratings Symbol Values min. max. 2.3 2.3 2.3 95 V V V %
1) 1) 1) 1)
Unit
Note/Test Condition
Voltage on any pins relative to VSS Voltage on VDD relative to VSS Voltage on VDD Q relative to VSS Storage Humidity (without condensation)
VIN, VOUT VDD VDDQ HSTG
- 0.5 - 1.0 - 0.5 5
1) Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability
Table 14 Parameter
Operating Conditions Symbol Values min. max. +55 +95 +100 +105 90 C C C kPa %
5) 1)2)3)4)
Unit
Notes
DIMM Module Operating Temperature Range (ambient) DRAM Component Case Temperature Range Storage Temperature Barometric Pressure (operating & storage) Operating Humidity (relative)
TOPR TCASE TSTG
PBar
0 0 - 50 +69 10
HOPR
1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs 2) Within the DRAM Component Case Temperature range all DRAM specification will be supported. 3) Above 85C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 s. 4) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below 85C case temperature before initiating self-refresh operation. 5) Up to 3000 m.
Table 15 Parameter
Supply Voltage Levels and DC Operating Conditions Symbol Values Min. Nom. 1.8 1.8 0.5 x VDDQ - - - Max. 1.9 1.9 0.51 x VDDQ 3.6 V V V V V V A
3)
Unit
Notes 1) 2)
Device Supply Voltage Output Supply Voltage Input Reference Voltage SPD Supply Voltage DC Input Logic High DC Input Logic Low In / Output Leakage Current
VDD VDDQ VREF VDDSPD VIH (DC) VIL (DC) IL
1.7 1.7 0.49 x VDDQ 1.7
VREF + 0.125
- 0.30 -5
VDDQ + 0.3 VREF - 0.125
5
1) Under all conditions, VDDQ must be less than or equal to VDD 2) Peak to peak AC noise on VREF may not exceed 2% VREF (DC). VREF is also expected to track noise in VDDQ. 3) Input voltage for any connector pin under test of 0 V VIN VDDQ + 0.3 V; all other pins at 0 V. Current is per pin
Data Sheet
23
Rev. 1.0, 2004-10 09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
Electrical Characteristics
Table 16
Speed Grade Definition Speed Bins DDR2-533C -3.7 4-4-4 Symbol @ CL = 3 @ CL = 4 @ CL = 5 Min. 5 3.75 3.75 45 60 15 15 Max. 8 8 8 70000 -- -- -- DDR2-400B -5 3-3-3 Min. 5 5 5 40 55 15 15 Max. 8 8 8 70000 -- -- -- Unit Notes
Speed Grade IFX Sort Name CAS-RCD-RP latencies Parameter Clock Frequency
tCK
-- ns ns ns ns ns ns ns
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time
tCK tCK tCK tRAS tRC tRCD tRP
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only. 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode 3) Inputs are not recognized as valid until recognized as low. 5)
VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
4) The output timing reference voltage level is VTT.
tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C Symbol -3.7 DDR2-533 4-4-4 Min. Max. +500 -- 0.55 -- 0.55 -- -- -500 2 0.45 3 0.45 WR + tRP -5 DDR2-400 3-3-3 Min. -600 2 0.45 3 0.45 WR + tRP Max. +600 -- 0.55 -- 0.55 -- -- ps Unit Notes1)
Table 17 Parameter
DQ output access time from CK / CK tAC CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time Minimum time clocks remain ON after CKE asynchronously drops LOW DQ and DM input hold time (differential data strobe) DQ and DM input hold time (single ended data strobe)
tCCD tCH tCKE tCL tDAL tDELAY
tCK tCK tCK tCK tCK
ns
tIS + tCK + tIH
tIS + tCK + tIH
275 25 0.35 -500
tDH(base) 225 tDH1(base) -25
0.35 -450
-- -- -- +450
-- -- -- +500
ps ps
DQ and DM input pulse width (each tDIPW input) DQS output access time from CK / CK Data Sheet
tCK
ps
tDQSCK
24
Rev. 1.0, 2004-10 09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
Electrical Characteristics Table 17 Parameter Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C (cont'd) Symbol -3.7 DDR2-533 4-4-4 Min. DQS input low (high) pulse width (write cycle) DQS-DQ skew (for DQS & associated DQ signals) Max. -- 300 0.35 -- WL - 0.25 -5 DDR2-400 3-3-3 Min. 0.35 -- Max. -- 350 Unit Notes1)
tDQSL,H tDQSQ
tCK
ps
Write command to 1st DQS latching tDQSS transition DQ and DM input setup time (differential data strobe)
WL + 0.25 WL - 0.25 WL + 0.25 tCK -- -- -- -- 150 25 0.2 0.2 -- -- -- -- ps ps
tDS(base) 100
DQ and DM input setup time (single tDS1(base) -25 ended data strobe) DQS falling edge hold time from CK tDSH (write cycle) DQS falling edge to CK setup time (write cycle) Clock half period CK / CK 0.2 0.2
tCK tCK
tDSS
tHP Data-out high-impedance time from tHZ
MIN. (tCL, tCH) -- 375 0.6
MIN. (tCL, tCH) -- 475 0.6
tAC.MAX
-- --
tAC.MAX
-- --
ps ps
Address and control input hold time tIH(base) Address and control input pulse width (each input) DQ low-impedance time from CK / CK DQS low-impedance from CK / CK Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS Data hold skew factor Average periodic refresh Interval Auto-Refresh to Active/AutoRefresh command period Precharge-All (4 banks) command period Read preamble Read postamble Active bank A to Active bank B command period Internal Read to Precharge command delay
tIPW
tCK
ps ps ps
Address and control input setup time tIS(base)
250 2 x tAC.MIN
--
350 2 x tAC.MIN
--
tLZ(DQ) tLZ(DQS) tMRD tOIT tQH tQHS tREFI tRFC tRP tRPRE tRPST tRRD tRTP
tAC.MAX tAC.MAX
-- 12 -- 400 7.8 3.9 -- -- 1.1 0.60 -- -- --
tAC.MAX tAC.MAX
-- 12 450 7.8 3.9 -- -- 1.1 0.60 -- -- --
tAC.MIN
2 0
tAC.MIN
2 0 -- -- -- 105
tCK
ns ps s s ns ns
2) 3)
tHP - tQHS
-- -- -- 105
tHPQ - tQHS --
tRP + 1tCK
0.9 0.40 7.5 10 7.5
tRP + 1tCK
0.9 0.40 7.5 10 7.5
tCK tCK
ns ns ns
Data Sheet
25
Rev. 1.0, 2004-10 09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
Electrical Characteristics Table 17 Parameter Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C (cont'd) Symbol -3.7 DDR2-533 4-4-4 Min. Write preamble Max. -- 0.60 -- 0.35xtCK 0.40 15 -5 DDR2-400 3-3-3 Min. 0.35xtCK 0.40 15 Max. -- 0.60 -- Unit Notes1)
tWPRE Write postamble tWPST Write recovery time for write without tWR
Auto-Precharge WR
tCK tCK
ns
Write recovery time for write with Auto-Precharge Internal Write to Read command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to Read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command
tWR/tCK
7.5 2 -- --
tWR/tCK
10 2 -- --
tCK
ns
tWTR tXARD tXARDS tXP tXSNR
tCK tCK tCK
ns
6 - AL
--
6 - AL
--
2
--
2
--
tRFC +10
200
-- --
tRFC +10
200
-- --
Exit Self-Refresh to Read command tXSRD
2) 0 TCASE 85 C 3) 85 C < TCASE 95 C
tCK
1) For details and notes see the relevant INFINEON component data sheet
Table 18 Symbol
ODT AC Electrical Characteristics and Operating Conditions Parameter / Condition ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off Values Min. Max. 2 2 Unit Notes
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
tCK
ns ns
1)
tAC.MIN tAC.MAX + 1 ns tAC.MIN + 2 ns 2 tCK + tAC.MAX + 1 ns
2.5 2.5
tCK
2)
tAC.MIN tAC.MAX + 0.6 ns ns ODT turn-off (Power-Down Modes) tAC.MIN + 2 ns 2.5 tCK + tAC.MAX + 1 ns ns ODT to Power Down Mode Entry Latency 3 -- tCK ODT Power Down Exit Latency 8 -- tCK
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measure from tAOND. 2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
Data Sheet
26
Rev. 1.0, 2004-10 09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
SPD Codes
5
Table 19
SPD Codes
SPD Codes for HYS64T[32/64/128]0xxHDL-3.7-A HYS64T128021HDL-3.7-A 1 GByte x64 2 Ranks (x8) Rev. 1.1 HEX 80 08 08 0E 0A 61 40 00 05 3D 50 00 82 08 00 00 0C 04 38 00 04 00 01 3D 50 Rev. 1.0, 2004-10 09122003-FTXN-KM26 HYS64T32000HDL-3.7-A HYS64T64020HDL-3.7-A 512 MB x64 2 Ranks (x16) Rev. 1.1 HEX 80 08 08 0D 0A 61 40 00 05 3D 50 00 82 10 00 00 0C 04 38 00 04 00 01 3D 50
Product Type
Organization
256 MB x64 1 Rank (x16)
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level
PC2-4200S-444 PC2-4200S-444 PC2-4200S-444 Rev. 1.1 HEX 80 08 08 0D 0A 60 40 00 05 3D 50 00 82 10 00 00 0C 04 38 00 04 00 01 3D 50
tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes
tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns]
Data Sheet
27
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
SPD Codes Table 19 SPD Codes for HYS64T[32/64/128]0xxHDL-3.7-A (cont'd) HYS64T128021HDL-3.7-A 1 GByte x64 2 Ranks (x8) Rev. 1.1 HEX 50 60 3C 1E 3C 2D 80 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 00 51 78 3E 2E 1E Rev. 1.0, 2004-10 09122003-FTXN-KM26 HYS64T32000HDL-3.7-A HYS64T64020HDL-3.7-A 512 MB x64 2 Ranks (x16) Rev. 1.1 HEX 50 60 3C 28 3C 2D 40 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 00 53 72 52 2B 1D
Product Type
Organization
256 MB x64 1 Rank (x16)
Label Code JEDEC SPD Revision Byte# 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Description
PC2-4200S-444 PC2-4200S-444 PC2-4200S-444 Rev. 1.1 HEX 50 60 3C 28 3C 2D 40 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 00 53 72 52 2B 1D 28
tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
PLL Re-lock Time
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q ( (DT2Q, RDIMM) T2P (DT2P)
Data Sheet
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
SPD Codes Table 19 SPD Codes for HYS64T[32/64/128]0xxHDL-3.7-A (cont'd) HYS64T128021HDL-3.7-A 1 GByte x64 2 Ranks (x8) Rev. 1.1 HEX 1E 24 17 34 1E 20 00 00 00 00 11 D2 C1 00 xx 36 34 54 31 32 38 30 32 31 48 44 4C Rev. 1.0, 2004-10 09122003-FTXN-KM26 HYS64T32000HDL-3.7-A HYS64T64020HDL-3.7-A 512 MB x64 2 Ranks (x16) Rev. 1.1 HEX 1D 23 16 36 1C 30 00 00 00 00 11 BC C1 00 xx 36 34 54 36 34 30 32 30 48 44 4C 33
Product Type
Organization
256 MB x64 1 Rank (x16)
Label Code JEDEC SPD Revision Byte# 52 53 54 55 56 57 58 59 60 61 62 63 64 65 -71 72 73 74 75 76 77 78 79 80 81 82 83 84 Description T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W S Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2 - 8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12
PC2-4200S-444 PC2-4200S-444 PC2-4200S-444 Rev. 1.1 HEX 1D 23 16 36 1C 30 00 00 00 00 11 BB C1 00 xx 36 34 54 33 32 30 30 30 48 44 4C 33
Data Sheet
29
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
SPD Codes Table 19 SPD Codes for HYS64T[32/64/128]0xxHDL-3.7-A (cont'd) HYS64T128021HDL-3.7-A 1 GByte x64 2 Ranks (x8) Rev. 1.1 HEX 33 2E 37 41 20 20 2x xx xx xx xx 00 Rev. 1.0, 2004-10 09122003-FTXN-KM26 HYS64T32000HDL-3.7-A HYS64T64020HDL-3.7-A 512 MB x64 2 Ranks (x16) Rev. 1.1 HEX 2E 37 41 20 20 20 2x xx xx xx xx 00
Product Type
Organization
256 MB x64 1 Rank (x16)
Label Code JEDEC SPD Revision Byte# 85 86 87 88 89 90 91 92 93 94 95 - 98 Description Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1 - 4)
PC2-4200S-444 PC2-4200S-444 PC2-4200S-444 Rev. 1.1 HEX 2E 37 41 20 20 20 2x xx xx xx xx 00
99 -127 Not used
Data Sheet
30
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
SPD Codes
Table 20
SPD Codes for HYS64T[32/64/128]0xxHDL-5-A HYS64T128021HDL-5-A 1 GByte x64 2 Ranks (x8) PC2-3200S- 333 Rev. 1.1 HEX 80 08 08 0E 0A 61 40 00 05 50 60 00 82 08 00 00 0C 04 38 00 04 00 01 50 60 50 60 Rev. 1.0, 2004-10 09122003-FTXN-KM26 HYS64T32000HDL-5-A HYS64T64020HDL-5-A 512 MB x64 2 Ranks (x16) PC2-3200S- 333 Rev. 1.1 HEX 80 08 08 0D 0A 61 40 00 05 50 60 00 82 10 00 00 0C 04 38 00 04 00 01 50 60 50 60
Product Type
Organization
256 MB x64 1 Rank (x16)
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level
PC2-3200S- 333 Rev. 1.1 HEX 80 08 08 0D 0A 60 40 00 05 50 60 00 82 10 00 00 0C 04 38 00 04 00 01 50 60 50 60 31
tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes
tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns]
Data Sheet
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
SPD Codes Table 20 SPD Codes for HYS64T[32/64/128]0xxHDL-5-A (cont'd) HYS64T128021HDL-5-A 1 GByte x64 2 Ranks (x8) PC2-3200S- 333 Rev. 1.1 HEX 3C 1E 3C 28 80 35 47 15 27 3C 28 1E 00 00 37 69 80 23 2D 00 51 78 32 24 1E 1B 1E Rev. 1.0, 2004-10 09122003-FTXN-KM26 HYS64T32000HDL-5-A HYS64T64020HDL-5-A 512 MB x64 2 Ranks (x16) PC2-3200S- 333 Rev. 1.1 HEX 3C 28 3C 28 40 35 47 15 27 3C 28 1E 00 00 37 69 80 23 2D 00 51 72 42 23 1D 19 1C
Product Type
Organization
256 MB x64 1 Rank (x16)
Label Code JEDEC SPD Revision Byte# 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Description
PC2-3200S- 333 Rev. 1.1 HEX 3C 28 3C 28 40 35 47 15 27 3C 28 1E 00 00 37 69 80 23 2D 00 51 72 42 23 1D 19 1C
tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
PLL Re-lock Time
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q ( (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) 32
Data Sheet
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
SPD Codes Table 20 SPD Codes for HYS64T[32/64/128]0xxHDL-5-A (cont'd) HYS64T128021HDL-5-A 1 GByte x64 2 Ranks (x8) PC2-3200S- 333 Rev. 1.1 HEX 17 28 1B 1E 00 00 00 00 11 1C C1 00 xx 36 34 54 31 32 38 30 32 31 48 44 4C 35 41 Rev. 1.0, 2004-10 09122003-FTXN-KM26 HYS64T32000HDL-5-A HYS64T64020HDL-5-A 512 MB x64 2 Ranks (x16) PC2-3200S- 333 Rev. 1.1 HEX 16 2E 1A 2D 00 00 00 00 11 04 C1 00 xx 36 34 54 36 34 30 32 30 48 44 4C 35 41 20
Product Type
Organization
256 MB x64 1 Rank (x16)
Label Code JEDEC SPD Revision Byte# 54 55 56 57 58 59 60 61 62 63 64 65 - 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 Description T3P.slow (DT3P slow) T4R (DT4R) / T4R4W S Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2 - 8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14
PC2-3200S- 333 Rev. 1.1 HEX 16 2E 1A 2D 00 00 00 00 11 03 C1 00 xx 36 34 54 33 32 30 30 30 48 44 4C 35 41 20
Data Sheet
33
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
SPD Codes Table 20 SPD Codes for HYS64T[32/64/128]0xxHDL-5-A (cont'd) HYS64T128021HDL-5-A 1 GByte x64 2 Ranks (x8) PC2-3200S- 333 Rev. 1.1 HEX 20 20 20 20 2x xx xx xx xx 00 Rev. 1.0, 2004-10 09122003-FTXN-KM26 HYS64T32000HDL-5-A HYS64T64020HDL-5-A 512 MB x64 2 Ranks (x16) PC2-3200S- 333 Rev. 1.1 HEX 20 20 20 20 2x xx xx xx xx 00
Product Type
Organization
256 MB x64 1 Rank (x16)
Label Code JEDEC SPD Revision Byte# 87 88 89 90 91 92 93 94 95 - 98 99 - 127 Description Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1 - 4) Not used
PC2-3200S- 333 Rev. 1.1 HEX 20 20 20 20 2x xx xx xx xx 00
Data Sheet
34
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
Package Outlines
6
Package Outlines
67.6 63.6 0.1 3.8 MAX.
1.8 0.05
4 0.1
(2.15)
1
17.55 0.1 2.7 0.1 (1.5)
(2.45)
100
30
10.1
0.15
11.4 0.1
47.4 0.1 (1.8)
(2.45)
4 0.1
2.4 0.1 10.1 101
(2.15)
6 0.1 20 0.1
200
2 MIN.
Detail of contacts
0.25 -0.18
0.45 0.03 0.6 0.1 Burnished, no burr allowed
GLD09649
Figure 5
Package Outline Raw Card A L-DIM-200-31
Data Sheet
2.55
35
Rev. 1.0, 2004-10 09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
Package Outlines
67.6 63.6 0.1 3.8 MAX.
1.8 0.05
4 0.1
(2.15)
1
17.55 0.1 2.7 0.1 (1.5)
(2.45)
100
30
10.1
0.15
11.4 0.1
47.4 0.1 (1.8)
(2.45)
2.4 0.1 10.1 101
(2.15)
4 0.1
200
6 0.1 20 0.1
2 MIN.
Detail of contacts
0.25 -0.18
0.45 0.03 0.6 0.1 Burnished, no burr allowed
GLD09648
Figure 6
Package Outline Raw Card C L-DIM-200-30
Data Sheet
2.55
36
Rev. 1.0, 2004-10 09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
Package Outlines
67.6 63.6 0.1 3.8 MAX.
1.8 0.05
4 0.1
(2.15)
1
17.55 0.1 2.7 0.1 (1.5)
(2.45)
100
30
10.1
0.15
11.4 0.1
47.4 0.1 (1.8)
(2.45)
4 0.1
2.4 0.1 10.1 101
(2.15)
6 0.1 20 0.1
200
2 MIN.
Detail of contacts
0.25 -0.18
0.45 0.03 0.6 0.1 Burnished, no burr allowed
GLD09675
Figure 7
Package Outline Raw Card F - L-DIM-200-34
Data Sheet
2.55
37
Rev. 1.0, 2004-10 09122003-FTXN-KM26
HYS64T[32/64/128]0xxHDL-[3.7/5]-A Small Outline DDR2 SDRAM Modules
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
7
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
Infineon's nomenclature uses simple coding combined with some proprietary coding. Table 21 provides examples for module and component product type number as well as the field number. The detailed field description together with possible values and coding explanation is listed for modules in Table 22 and for components in Table 23. Table 21 Nomenclature Fields and Examples Field Number 1 Micro-DIMM DDR2 DRAM Table 22 1 2 3 4 HYS HYB 2 64 18 3 T T 4 64 512 5 0 16 6 2 7 0 0 8 K A 9 M C 10 -5 -5 11 -A
Example for
DDR2 DIMM Nomenclature Values Coding HYS 64 72 T 32 64 128 256 0 .. 9 Constant Non-ECC ECC DDR2 256 MByte 512 MByte 1 GByte 2 GByte look up table 1, 2, 4 look up table look up table SO-DIMM Micro-DIMM Registered Unbuffered PC2-4200 4-4-4 PC2-3200 3-3-3 First Second
Field Description INFINEON Modul Prefix Module Data Width [bit] DRAM Technology Memory Density per I/O [Mbit]; Module Density1)
1) Multiplying "Memory Density per I/O" with "Module Data Width" and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes as listed in column "Coding".
Table 23 1 2 3 4
DDR2 DRAM Nomenclature Values Coding HYB Constant SSTL1.8 DDR2 256 Mbit 512 Mbit 1 Gbit 2 Gbit x4 x8 x16 look up table First Second FBGA, lead-containing FBGA, lead-free DDR2-533C DDR2-400B
Field Description INFINEON Component Prefix DRAM Technology
Interface Voltage [V] 18 T Component Density 256 [Mbit] 512 1G 2G
5 6 7 8 9
Raw Card Generation
Number of Module 0, 2, 4 Ranks Product Variations 0 .. 9 Package, Lead-Free Status Module Type A .. Z D M R U
5+6 Number of I/Os
40 80 16
7 8 9
Product Variations Die Revision Package, Lead-Free Status Speed Grade N/A for Components
0 .. 9 A B C F
10 11
Speed Grade Die Revision
-3.7 -5 -A -B
10 11
-3.7 -5
Data Sheet
38
Rev. 1.0, 2004-10 09122003-FTXN-KM26
www.infineon.com
Published by Infineon Technologies AG

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